Work in progress: 400W fully digital class D amplifier with DSP

This is a continuation of the 1000W class D amp design. It may be a good idea to read that article first as this is a highly modified version of that previous design and it describes many of the reasoning behind my design choices.

1000W amp: Why did the project fail?

One thing I believe is important is admitting failure. We are all people and we are not all perfect - we make mistakes. I admit that I failed at making the amplifier I wanted to make operational to the way I want it. 

So the issues are:

-No sound from DAC (PCM5242)

-Noise from ADC (PCM1802) - fixed (cause is a oscillating AMS1117-5V linear regulator)

-Amp output stage not confirmed

Working:

- PCM2706 (works perfectly) - ASRC works correctly to convert USB sample rate to 48K (DSP native)

- ADC (PCM1802 works partially) - fixed now

- Bluetooth (QCC5125 works) - ASRC works correctly to convert 44.1K to 48K (DSP native)

These are the issues discovered in later test. Here are some flaws in the design:

-Use of MCLK line: the DACs output loud popcorn noise if I use a external PCM5102 with the amp for output (very loud and disturbing, like 0db loud) occasionally with SigmaStudio after flashing some DSP code. Seems like some issues with master clock as the issue disappears in 3 wire I2S mode. The MCLK lines are noisy from a EMI standpoint. Thus, the DACs should be set as master instead of slave.

-Resistor source selector designed wrongly

-Use of QFN packages (a nightmare to solider onto PCB!)

Addressing the flaws in the next design:

The basic design philosophy goes as follow:

- No QFN!

- Simpler is better

- Larger SMT components are better

And below is how I addressed those points:

Output stage + DAC change: instead of using a PCM5242 + TPA3255, I replaced it with a single TAS5830 IC. This takes in a digital I2S input, does not require a reset circuit, DAC, and needs minimal external circuits. The benefits are as follows:

    - Lower idle current draw, due to the use of 1PSW modulation compared to BD (TPA3255). The heatsink and inductors are literally barely warm after blasting full volume for a while, remarkable!

    - Less concerns with grounding as the Amp IC is fully digital, following single ground as shown in EVM.

    - SW mode is very powerful and allows for diagnostics, config, and even level reading (as well as DSP)

    - Lower external component complexity: No more analog input circuitry! Just decoupling caps, some config resistors, and output filters!

    -Potential for more "marketing" - ooh fully digital audio stream!

    - TAS5828 validated with ADAU1452. Since the TAS5830 shares the same pinout + registers as the TAS5828, the TAS5830 will work with the DSP. Here is the source of validation: https://oshwhub.com/lbl66666/adau1452-tas5828-gong-fang

ADC IC changed: I used a PCM1863 IC that allows for software control and has higher SNR than the PCM1802. The IC also allows for using the PGA to change gain without using external op-amps, in addition to differential inputs. I also used a ultra low noise regulator as the previous one was oscillating (AMS1117-5V), don't use that regulator please!

Change in components used: Again NO QFN! I joke around with people with how I have "beef" with QFN components. I say that if I need to solider it by hand, but I am ok with such if using pick and place. A TSSOP component takes me at most 5 minutes while the QFN package for the PCM5242 took me and my friend over 1 hour without it working! If you want to handsolider or even hand pick and place QFN, my advice is please don't, you are doing yourself a disfavor.

In addition, I used 1206 and 0805 when possible. While I don't have problems with 0603, it takes a bit longer for me to do such components, but I can do 0805+ pretty fast. Just like with QFN please don't do anything smaller than 0603, your are putting yourself in a pit of upset if you do (at least it does for me).

Added a MCU: I used a RP2350 for the MCU to control everything. It is overkill but everything in Jason's world has to be overkill.

Now here are the disadvantages of this new design:

- Each channel will need it's own IC (In PBTL) to output 100W at 4R (29V), increasing IC count

- Power output is reduced from 140W to 100W for THD+N=1% measurements

- SW mode of both amp and ADC IC adds complexity from software standpoint (MCU)

- Grounding? Ground bounce issues? No, the EVM works too well, forget about those issues. But I did add local bulk decoupling caps similar to the EVM to reduce ground bounce caused by the di/dt of the amps, compared to having them on the left/right with the old design

Changes to the functionality itself:

Notice that the amp only has 4 channels, not 6. The 2 other channels are removed since it is not really necessary for proper listening. 

The reasons are below:

- Most content is mixed for 2 channel, not 4.

- Bluetooth and USB does not support 4 channel streaming, instead it has to be upscaled. This reduces audio fidelity and increases audible artifacts to the listener.

- If I feed identical content to the rear channels, comb filtering will happen due to constructive/destructive interference at different frequancies - resulting in a headache inducing sound

- 5.1 content requires a dedicated decoder, and we don't have a center channel

- Having 2 additional speakers require the subwoofer to be driven harder to maintain balance in the bass region (and it may not be even able to keep up)

- Larger PCB size (and more components too)

- Higher PSU power delivery requirements (and it gets much harder to find a non-sketchy power supply. I currently use a Meanwell RSP-500-27 that I set to 26-28V)

But anyways, lets discuss the design:

So similar file structure to the previous design, but as you can see we use a fully digital amplifier stage now, which removes the DAC section that is previously there. The digital I2S audio signal is directly routed from the ADAU1466 DSP module straight to the amplifier chips. Since we have 1 less ADC, I exposed that extra I2S input line for external sources that could be added in later if I want (AES3/Dante decoder??) if I need. One of the I2S inputs are reserved for Bluetooth (provided by a QCC5125 module). 

Starting with the ADC design, the design changes over to the PCM1863 from the PCM1802. I still used a separate ground plane as I was concerned that the return currents (and ground bounce from both DSP and class D amps) are going to cause noise on the sensitive analog signals. I allowed for both single ended and differential inputs. Since the ADC is going to be a master clock slave, the crystal is not used.

Nothing changed on this circuit, it works really well!

I did change the above however. In fact this is the biggest change. As I mentioned earlier I am using a fully digital amp IC. In addition, each amp gets it's own PBTL bridged chip, which allows the amp to drive the output down to 3 ohms without stability issues, though I still stick with a 4 ohm rating since the inductors cannot handle such high current. As you can see, there is a significant reduction in component count here, which is good! There are 4 of these circuits. I allowed myself to use 0R resistors to set hardware settings and added DNP zobel networks just in case I need them. I still had clamp diodes to prevent damage from no-load conditions.

And now for the microcontroller! I am using a RP2350 microcontroller to drive the I2C (not I2S) to talk to the 4 AMP ICs, the ADC, and talking to the HMI using UART. The MCU enables and disables the PDN pin, sets the config, does PWM sync, and more. As I am still working on code, this part is still WIP.

Lastly, here is power. So the AMPs are powered off the same 3.3V as the DSP and other "dirty stuff". So you may ask yourself if I am crazy to do so especially for a low noise design. The answer is ... no. The reason why is that if you look at the power tree diagram for the TAS5830s, the 3.3V is actually just powering the onboard DSP. The power derived for the internal DAC comes from the PVDD power supply rails (the 29V or so of power). Since a DSP is digital, I don't foresee any issues with an increase in noise as it shouldn't care about ripple). In addition, my switcher switches at around 1.5 megahertz, so ripple should be low. 

However, what can't use dirty power is the 3.3V regulator for the ADC. This is critical as having stable power is important to maintaining a high SNR. Although the ADC has a PSRR of around 80dB, I still wanted the lowest possible noise. To achieve that, I needed to choose a 3.3V regulator with ultra low noise and very high PSRR numbers, and the regulator from Analog Devices should achieve that.

In addition, I lowered the first high current regulator from 12V to 5V. In addition to being able to remove one switching regulator, I also am using 5V PWM fans. Thus the need of a 12V power rail is not present and I used 5V instead.

Lastly, many would ask me, "Jason what are you going to do about the noisy spikes caused by a fan motor"? My response is.... decoupling capacitors! I once had issues with a HMI display causing a slight increase in noise in a PGA2311 board, and adding decoupling capacitors helped in that case. The same remedy can be used here as there was a whole paper I found online where large (47-100uf) decoupling capacitors near + and - power output to the fan reduced the fan's motor noise on power to nothing. I would be doing the same here.

PCB layout:

All layers

Layer 1 - no copper

Layer 1 - with copper

Layer 2 - (GND plane) - with copper

Layer 3 - Power plane (3.3V and 5V) - with copper

Layer 4 - rear signal layer - without copper

Layer 4 - with copper

And oh yeah, EVMs!

Thanks to Dr. Fayed, I got to have this project funded under the SCALE program. Because of this, I was able to order 2 TAS5830EVMs and a PCM1863EVM to test out my connections and code. With that I learned a ton about these chips and software quirks I had to deal with.

I also learned about the issue of ground bounce from him and because of that (and following EVM guidelines as best as I can, I added local bulk capacitors below the board to smoothen the lower frequancy di/dt spikes caused by the switching class D amps.

TAS5830:

Issue 1: No library for the TAS5830 chips (Arduino IDE) - this was my first time actually doing I2C stuff by using the datasheet and not the Arduino library someone already wrote for these chips. Because of that, it was more tedious and difficult from before but I managed to get it to work

Issue 2: PWM synchronization headaches! I can't express how annoying it was to get this to work. I got all the code right but the amp sometimes just jumped into high Z when nothing was playing. Turns out, it always worked when I had stuff playing into the XMOS on the EVM and didn't work if no stuff was playing before hand. Why? It turns out that the TAS needs valid I2S clocks for the sync to work. My guess for this is that it uses the I2S clock as a sort of oscillator clock to keep track of some sort of period. Think of the GPIO sync pin as the sound that plays when runners can start running in a race and the I2S clocks as like the number of laps around the track. So there is no sort of oscillator for the AMP to know where it is at in time without clocks. 

However, it took me a while to figure this out. But issues disappeared when I connected it to my DSP board because it outputs stable clocks, no matter with or without stuff playing. However, it still goes to high Z on reset, but I have a way around that

Issue 3: Pops and crackles caused by I2S signals. This was caused by my I2S lines being too long between the EVMs and the DSP, but was resolved with termination resistors on the DSP transmitter end and changing the slew rate for the DSP to lowest and drive strength to max.